ARINDAM BANERJEE
ARINDAM BANERJEE
Designation: Assistant Professor, Computer Science and Engineering (School Of Engineering & Technology), Adamas University.
Email ID : banerjee.arindam1@gmail.com
Educational Qualifications :
Working Experience :
Publications :
A. Banerjee, D. K. Das, “The design of reversible multiplier using ancient Indian mathematics”, ISED-2013, pages- 31-35, December, 2013, Singapore.
A. Banerjee, D. K. Das, “Squaring in reversible logic using iterative structure”, East West Design and Test Symposium, 2014, Ukrain.
A. Banerjee, D. K. Das, “The Design of Reversible Signed Multiplier using Ancient Indian Mathematics”, Journal of Low Power Electronics, vol. 11, October, 2015, pp. 467-478. (SCI(M), ScopusI.F. – 0.84)
A. Banerjee, D. K. Das, “A New Squarer Design with Reduced Area and Delay”, IET Computers and Digital Techniques, vol. 10, issue 5, February, 2016, pp. 205-214. (SCI(E), I.F. – 0.515)
A. Banerjee, D. K. Das, “Squaring in Reversible Logic using Zero Garbage and Reduced Ancillary inputs”, Int. Symp. On VLSI Design, January, 2016.
A. Banerjee, D. K. Das, “Squarer Design with Reduced Area and Delay”, VLSI Design and Test Symp., May, 2015.
A. Banerjee, D. K. Das, “A New ALU Architecture Design using Reversible Logic”, Int. Symp. On Electronic Design (ISED-2016), December, 2016.
A. Banerjee, D. K. Das, “A Novel ALU Circuit based on Reversible Logic”, Journal of Circuits, Systems and Computers, World Scientific Publisher, Vol. 29, No. 11, 15th September, 2020.(SCI)
Arindam Banerjee, “Detection and Elimination of Single and Multiple Missing Gate Fault(SMGF/MMGF) of Reversible Arithmetic Circuits”, Power Devices and IoT for Intelligent System Design, Scrivener Publishing LLC, 2024, pp. 271-302 (proof reading).
Arindam Banerjee, “Analysis of Inheritance of Criminal Behavior from the Parents Using Genetic Algorithm”, Smart Innovation, Systems and Technologies, chapter 30, vol. 405, Springer Nature, 2024.
Arindam Banerjee, Aniruddha Ghosh, Mainuck Das, “Design of A Novel Signed Binary Subtractor using Quantum Gates”, Journal of Quantum Computing, Tech Science Press, vol. 4, no. 3, 2023.
Arindam Banerjee, “Optimized Test Pattern Generation for Single Missing Gate Fault Detection in Reversible Arithmetic Circuits”, IEEE-EDKCON (International Conference)-2022,November, 2022.
Arindam Banerjee, Aniruddha Ghosh, Mainuck Das, SK Suman, Arvik Sai, “Memristor Based Multiplier and Squarer of some numbers of the form 10l ± m”, Journal of The Institution of Engineers (India): Series B (IEIB), vol. 103, pp. 1239–1247, 2022 (published, DOI: 10.1007/s40031-022-00717-7).
Arindam Banerjee and Debesh Kumar Das, “Arithmetic Circuits Using Reversible Logic: A Survey Report”, Springer, LNCS. (Book chapter)
A. Banerjee, M. Das, A. Ghosh, “AI Based Online Data Segregation Method under COVID Situation”, IOCER- 2020, 8-9 October, 2020 (published in IOP (Journal of Physics – Conference Series)
A. Banerjee, S. Bhattacharyya, A. Deyasi, “High Speed Reconfigurable ALU Design for Radix (2n±m)”, Advances in Industrial Engineering and Management, American Scientific Publishers, vol. 5, no. 2, 2016, pp. 183-187, 2016. (ISSN: 2222-7059 (Print); E-ISSN: 2222-7067 (Online))
S. Pal, A. Banerjee, S. Bhattacharyya, “Optical Network Based RNS Multiplier in (2n-1) Radix System using SOAMZI”, NCRAST-2016 at Heritage Institute of Technology.
A. Banerjee, S. Pal, S. Bhattacharyya, D. K. Das, “Memristor Based Modulo Multiplier Design For (2n-1) and 2n Radix”, DevIC-2017, Kalyani Govt. Engineering College. (IEEE xplore)
A. Banerjee, S. Bhattacharyya, A. Deyasi, “Synthesis of High Speed Multi-valued ALU for (2n±m) Radix”, MCCS-2017, Ranchi. (Springer, Book chapter)
A. Banerjee, S. Bhattacharyya, A. Deyasi, “Fast Squaring Technique for Radix Vicinity Numbers for Radix (2n±m) with reduced Computational Complexity”, NCCS-2017, Ranchi. (Springer, Book chapter)
A. Banerjee, S. Pal, S. Bhattacharyya, D. K. Das, “Memristor Based MAC Architecture Design For (2n-1) and 2n Radix”, Journal of Active and Passive Electronic Devices, Old City Publishing, Philadelphia, Vol. 0, pp. 1-19, 2017 (SCI(M), ISSN: 1555-0281 (print), ISSN: 1555-029X (online)).
A. Banerjee, A. Ghosh, M. Das, SK Suman, A. Sain, “Memristor Based Fast Decimal Squaring of some numbers of the form 10l±m”, FEMAS-2019, October, 2019 (Accepted and Presented).
Prabir Kumar Saha, Arindam Banerjee, AnupDandapat, “High Speed Low Power Complex Multiplier Design Using Parallel Adders and Subtractors”, International Journal on Electronic and Electrical Engineering, (IJEEE), Vol 07, No. 11 Page No. 38-46, 2009.
Prabir Kumar Saha, Arindam Banerjee and A. Dandapat ,“Low power and High Speed Factorial Design in 22nm Technology”, accepted in AIP, 2010.
PrabirSaha, A. Banerjee, I. Banerjee and A. Dandapat, “High Speed Low Power Floating Point Multiplier Desiged Based on CSD (Canonical Sign Digit)”; Published in IJVED (National Journal).
P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya, “Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors”; Published in International Journal on Smart Sensing and Intelligent Systems.
Prabir Kumar Saha, Arindam Banerjee, A. Dandapat, P. Bhattacharyya, “ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics”, accepted in Microelectronics Journal, Elsevier.
A. Banerjee, M. Das, A. Ghosh, “FPGA Implementation of High Speed Numerically Controlled Oscillator for QAM architecture”, accepted in National Conference NCACD to be held at HIT, Haldia, West Bemgal, August, 2012.
A. Banerjee, R. Ghosh, S. Ghosh, “High Performance Novel Square root architecture using Ancient Indian Mathematics for High Speed Signal Processing”, accepted in National Conference NCACD to be held at HIT, Haldia, West Bemgal, August, 2012.
Prabir Saha, Arindam Banerjee, AnupDandapat and Partha Bhattacharya, “High Speed Vedic Multiplier for Decimal Number System”; accepted at VDAT-2012 organized by Bengal Engineering and Science University, 2012.
Arindam Banerjee, Atin Mukherjee and Debesh Choudhury, “VHDL Implementation of Spatial Fourier Processing”, Accepted in ICONTOP-2012, held at Calcutta University, January, 2012.
Arindam Banerjee, Atin Mukherjee, Prabir K. Saha and Debesh Choudhury, “Computation of Fresnel Diffraction by VHDL”, Accepted in FOP-11, held at IIT-Delhi, December, 2011.
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, AnupDandapat, “Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications”; accepted at ISED-2011 organized at Kochi.
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, AnupDandapat, “High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics”; accepted at Techsym-2011 organized by IIT Kharagpur.
Prabir Saha, A. Banerjee, I. Banerjee and A. Dandapat, “High Speed Low Power Floating Point Multiplier Design Based on CSD (Canonical Sign Digit)”; IEEE symposium on VLSI Design and Testing, VDAT-2010, Accepted.
Prabir Saha, Ranjana Roy, Ishita Banerjee, Arindam Banerjee, “FPGA Implementation of 2D convolution Architecture using Wave-front Array”; national seminar on Recent Trends in Engineering and Technology Including Non-Conventional Energy” April 10, 2010 at IMPS, Malda.
Prabir Kumar Saha, Arindam Banerjee and A. Dandapat, “Low power and High Speed Factorial Design in 22nm Technology” accepted at ICANN-2009 conducted by IIT Guwahati.